A1360, A1361,
and A1362
Delay to Clamp A large magnetic input step may cause the clamp
to overshoot its steady state value. The Delay to Clamp, t
CLP
, is
defined as: the time it takes for the output voltage to settle within
?% of its steady state value, after initially passing through its
steady state voltage, as shown in the following chart.
V
t
Magnetic Input
V
OUT
0
t
1
= time at which output voltage initially
reaches steady state clamp voltage
t
2
= time at which output voltage settles to
within 1% of steady state clamp voltage
Note: Times apply to both high clamp
(shown) and low clamp.
V
CLP(HIGH)
t
1
t
2
t
CLP
Quiescent Voltage Output In the quiescent state (no significant
magnetic field: B = 0 G), the output, V
OUT(Q)
, has a constant ratio
to the supply voltage, V
CC
, throughout the entire operating ranges
of V
CC
and ambient temperature, T
A
.
Guaranteed Quiescent Voltage Output Range The quiescent
voltage output, V
OUT(Q)
, can be programmed around its nominal
value of 2.5 V, within the guaranteed quiescent voltage range
limits: V
OUT(Q)
(min) and V
OUT(Q)
(max). The available guaranteed
programming range for V
OUT(Q)
falls within the distributions of
the initial, V
OUT(Q)init
, and the maximum programming code for
setting V
OUT(Q)
, as shown in the following diagram.
V
OUT(Q)
(max)
V
OUT(Q)
(min)
V
OUT(Q)init
(typ)
Guaranteed Output
Programming
Range, V
OUT(Q)
Distribution for
Max Code V
OUT(Q)
Distribution for
V
OUT(Q)init
Average Quiescent Voltage Output Step Size The average qui-
escent voltage output step size for a single device is determined
using the following calculation:
V
OUT(Q)maxcode
V
OUT(Q)init
2
n
1
Step
VOUT(Q)
=
.
(1)
where:
n is the number of available programming bits in the trim range,
2
n
1 is the value of the maximum programming code in the
range, and
V
OUT(Q)maxcode
is the quiescent voltage output at code 2
n
1.
Quiescent Voltage Output Programming Resolution The
programming resolution for any device is half of its programming
step size. Therefore, the typical programming resolution will be:
Err
PGVOUT(Q)
(typ)
= 0.5 ?/SPAN> Step
VOUT(Q)
(typ)
.
(2)
Quiescent Voltage Output Drift Through Temperature Range
Due to internal component tolerances and thermal considerations,
the quiescent voltage output, V
OUT(Q)
, may drift from its nominal
value over the operating ambient temperature, T
A
. For purposes
of specification, the Quiescent Voltage Output Drift Through
Temperature Range, V
OUT(Q)
(mV), is defined as:
V
OUT(Q)
V
OUT(Q)(TA)
V
OUT(Q)(25癈)
=
.
(3)
V
OUT(Q)
, should be calculated using the actual measured values
of V
OUT(Q)(TA)
and V
OUT(Q)(25癈)
, rather than programming target
values.
Sensitivity The presence of a south polarity magnetic field, per-
pendicular to the branded surface of the package face, increases
the output voltage from its quiescent value toward the supply
voltage rail. The amount of the output voltage increase is propor-
tional to the magnitude of the magnetic field applied. Conversely,
the application of a north polarity field decreases the output
voltage from its quiescent value. This proportionality is specified
as the magnetic sensitivity, Sens (mV/G), of the device, and it is
defined for bipolar devices as:
V
OUT(BPOS)
V
OUT(BNEG)
BPOS BNEG
Sens =
,
(4)
and for unipolar devices as:
V
OUT(BPOS)
V
OUT(Q)
BPOS
Sens =
,
(5)
where BPOS and BNEG are two magnetic fields with opposite
polarities.
Low-Noise Programmable Linear Hall Effect Sensor ICs with
Adjustable Bandwidth (50 kHz Maximum) and Analog Output
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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